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AS7C4096A-12TIN - 

SRAM, 4 Mbit, 512K x 8bit, 4.5V to 5.5V, TSOP, 44 Pins, 12 ns

AS7C4096A-12TIN - SRAM, 4 Mbit, 512K x 8bit, 4.5V to 5.5V, TSOP, 44 Pins, 12 ns

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AS7C4096A-12TIN   Datasheet
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Product Overview

The AS7C4096A-12TIN is a 5V 512k x 8-bit high-performance CMOS Static Random Access Memory (SRAM) organized as 524288 words x 8-bit. It is designed for memory applications where fast data access, low power and simple interfacing are desired. When CE is high the device enters standby mode. The device is guaranteed not to exceed 55mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable and chip enable. The data on the input pins I/O1-I/O8 is written on the rising edge of WE or CE. To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable or write enable. A read cycle is accomplished by asserting output enable and chip enable, with write enable high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode.
  • Pin compatible to AS7C4096
  • Center power and ground pins
  • Low power consumption - ACTIVE - 880mW/maximum at 10ns
  • Low power consumption - STANDBY - 55mW/maximum CMOS
  • Equal access and cycle times
  • TTL-compatible, 3-state I/O
  • Latch-up current >=200mA


Computers & Computer Peripherals, Industrial

Product Information

512K x 8bit
4.5V to 5.5V
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