S25FL128SAGNFI003

S25FL128SAGNFI003 is a 3.0V SPI flash memory. This device connects to a host system via a serial peripheral interface (SPI). Traditional SPI single bit serial input and output (single I/O or SIO) is supported as well as optional two-bit (Dual I/O or DIO) and four bit (quad I/O or QIO) serial commands. This multiple-width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for double data rate (DDR) read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock. The Eclipse architecture features a Page Programming Buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms. It offers high densities coupled with the flexibility and fast performance required by a variety of embedded applications. They are ideal for code shadowing, XIP, and data storage.

• 128Mbit density, 65nm MirrorBit process technology
• Advanced sector protection, auto boot mode, erase suspend/resume, program suspend/resume
• 2.7V to 3.6V / 1.65V to 3.6V VIO supply voltage
• Common flash interface (CFI) data for configuration information
• Quad-input page programming (QPP) for slow clock systems
• Cypress® 65 nm MirrorBit® Technology with Eclipse™ architecture
• Minimum 20 year data retention, one time program (OTP) array of 1024 bytes
• Automatic ECC -internal hardware error correction code generation with single bit error correction
• Industrial temperature range from -40°C to + 85°C, 8-contact WSON package