74AHC573PW,118

74AHC573PW,118 is an 8bit D-type transparent latch with 3-state outputs. This device features latch enable (LE) and output enable (active-low OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on active-low OE causes the outputs to assume a high-impedance OFF-state. Operation of the active-low OE input does not affect the state of the latches. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed-voltage environments. It features ESD protection (HBM JESD22-A114F exceeds 2000V, MM JESD22-A115-A exceeds 200V, CDM JESD22-C101E exceeds 1000V).

• Supply voltage range from 2.0V to 5.5V, balanced propagation delays
• All inputs have Schmitt-trigger action, overvoltage tolerant inputs to 5.5V
• High noise immunity, CMOS low power dissipation
• CMOS input level, latch-up performance exceeds 100mA per JESD 78 Class II Level A
• OFF-state output current is ±10.0μA max at (VI = VIH or VIL; VO = VCC or GND; VCC = 5.5V)
• Input leakage current is 2μA maximum at (VI = 5.5V or GND; VCC = 0V to 5.5V)
• Supply current is 80μA maximum at (VI = VCC or GND; IO = 0A; VCC = 5.5V)
• Input capacitance is 10pF maximum at (-40°C to +125°C)
• Propagation delay is 14ns maximum at (CL = 15pF, -40°C to +125°C)
• Operating temperature range from -40°C to +125°C, TSSOP20 package

Warnings

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.