74AUP1G157GW,125

74AUP1G157GW,125 is a low-power 2-input multiplexer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V). It complies with JEDEC standards JESD8-12 (0.8V to 1.3V), JESD8-11 (0.9V to 1.65V), JESD8-7 (1.65V to 1.95V), JESD8-5 (2.3V to 2.7V), JESD8C (2.7V to 3.6V).

• CMOS low power dissipation, high noise immunity
• Overvoltage tolerant inputs to 3.6V, low noise overshoot and undershoot <lt/> 10% of VCC
• IOFF circuitry provides partial power-down mode operation
• Low static power consumption; ICC = 0.9 µA (maximum)
• Latch-up performance exceeds 100mA per JESD 78 Class II
• Input leakage current is ±0.1μAmax at (Tamb = 25°C)
• Supply current is 0.5μA maximum at (VI = GND or VCC; IO = 0A; VCC = 0.8V to 3.6V)
• Input capacitance is 0.8pF typical at (VCC = 0V to 3.6V; VI = GND or VCC, Tamb = 25°C)
• Propagation delay is 12.6ns maximum at (VCC = 1.1V to 1.3V, CL = 5pF)
• Operating temperature range from -40°C to +125°C, TSSOP6 package

Warnings

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.