74AUP1G74DC,125

74AUP1G74DC,125 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (active-low SD) and reset (active-low RD) inputs, and complementary Q and active-low Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8V to 3.6V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V).

• CMOS low power dissipation, high noise immunity
• Overvoltage tolerant inputs to 3.6V, latch-up performance exceeds 100mA per JESD 78 Class II
• Low noise overshoot and undershoot <lt/> 10% of VCC, complies with JEDEC standards
• IOFF circuitry provides partial power-down mode operation
• Input leakage current is ±0.75μA maximum at (VI = GND to 3.6V; VCC = 0V to 3.6V)
• Power-off leakage current is ±0.75μA maximum at (VI or VO = 0V to 3.6V; VCC = 0V)
• Supply current is 1.4μA maximum at (VI = GND or VCC; IO = 0A; VCC = 0.8V to 3.6V)
• Propagation delay is 14.2ns maximum at (VCC = 1.1V to 1.3V, CL = 5pF)
• Operating temperature range from -40°C to +125°C
• VSSOP8 package

Warnings

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.