74LVC125APW-Q100J

74LVC125APW-Q100J is a quad non-inverting buffer/line driver with 3-state outputs (nY) that is controlled by the output enable input. A HIGH at n active-low OE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3V or 5V devices. When disabled, up to 5.5V can be applied to the outputs. This product has been qualified for the automotive electronics council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. It complies with JEDEC standard (JESD8-7A (1.65V to 1.95V), JESD8-5A (2.3V to 2.7V), JESD8-C/JESD36 (2.7V to 3.6V). It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V).

• 5V tolerant inputs/outputs for interfacing with 5V logic
• Wide supply voltage range from 1.65V to 3.6V
• CMOS low power consumption
• Direct interface with TTL levels
• Input leakage current is ±0.1μA typ at (VCC = 3.6V;VI = 5.5V or GND, -40°C to +85°C)
• Supply current is 0.1μA typ at (VCC = 3.6V;VI=VCC or GND;IO = 0A, -40°C to +85°C)
• Input capacitance is 4pF typical at (VCC = 0V to 3.6V;VI= GND to VCC)
• Propagation delay is 12ns typical at (VCC = 1.2V, -40°C to +85°C)
• Operating temperature range from -40°C to +125°C
• TSSOP14 package

Warnings

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.