74LVC1G175GV,125

74LVC1G175GV,125 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, active-low MR input, and Q output. The MR is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device in a mixed 3.3V and 5V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

• Wide supply voltage range from 1.65V to 5.5V, ESD protection
• High noise immunity, overvoltage tolerant inputs to 5.5V
• CMOS low power dissipation, direct interface with TTL levels
• OFF circuitry provides partial power-down mode operation
• Latch-up performance exceeds 250mA, complies with JEDEC standard
• Input leakage current is ±0.1μA typical at (VCC = 0V to 5.5V;VI = 5.5VorGND,Tamb = -40°C to +85°C)
• Supply current is 0.1μA typ at (VCC = 1.65V to 5.5V;IO = 0A;VI = 5.5V or GND,Tamb = -40°C to +85°C)
• Input capacitance is 2.5pF typ at (VCC = 3.3V; VI = GND to VCC, Tamb = -40°C to +85°C)
• Propagation delay is 4.9ns typ at (VCC = 1.65V to 1.95V, Tamb = -40°C to +85°C)
• Operating temperature range from -40°C to +125°C, TSOP6 package

Warnings

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.